1. Field of the Invention
The present invention relates to a semiconductor storage device, in particular a semiconductor storage device including a flip-flop type memory cell.
2. Description of Related Art
FIG. 21 shows a configuration of a SRAM (Static Random Access Memory) disclosed in Japanese Unexamined Patent Application Publication No. 2008-262637 (Yamagami), and FIG. 22 shows a configuration of a memory cell used in this SRAM. The reading operation of this SRAM is explained with reference to FIG. 23. FIG. 23 is a diagram for explaining a problem of the SRAM disclosed in Yamagami.
When a selected word line WL1 changes to a High level and access transistors 18 and 19 are thereby turned on, a potential at a cell node (connection point between a load transistor 11 and a drive transistor 16) that has retained Low data by bit lines BL1 and /BL1 pre-charged to the power-supply potential VDD is pulled down to Vnd.
If Vnd is larger than the logic threshold voltage Vth1 of the load transistor 11 and the drive transistor 16 that constitutes the cell inverter, the corruption of stored data could occur due to the inversion of the cell inverter, and thus leading to the malfunction of the SRAM (SNM (Static Noise Margin) failure).
Therefore, in Yamagami, pull-down circuits 30A and 30B that set the High level of the selected word line WL to a potential lower than the power-supply potential VDD are provided. In this way, the potential rise of the cell node retaining Low data is suppressed so that Vnd becomes smaller than the logic threshold voltage Vth1 of the cell inverter, and therefore an improvement is made against the occurrence of the stored data corruption (SNM failure).
Japanese Unexamined Patent Application Publication Nos. 2008-210443 and 2008-176907 also disclose similar techniques to make an improvement against the SNM failure by setting the High level of word lines to a potential lower than the power-supply potential. However, in these SNM improving techniques, although the reading characteristic is improved by setting the High level of selected word lines WL to a potential lower than VDD, the writing characteristic to the cells becomes worse on the contrary.
Writing is performed by driving a bit line BL1 to a Low level by a writing circuit so that the cell node that has been kept at a High level by the load transistor 11 is pulled down to a Low level through the access transistor 18 of the cell. However, since the potential of the selected word line WL1 has been lowered, the on-resistance of the access transistor 18 increases, and thus making pulling down the cell node to the Low level very difficult. Consequently, the data writing characteristic to the cell deteriorates.
Accordingly, it is conceivable that the High level of the selected word line WL1 should be set to the power-supply potential VDD only during the writing operation. However, when the word line WL1 is selected but the bit lines BL2 and /BL2 are not selected, it creates such a situation that cell access is performed for a memory cell 10C connected to the bit lines BL2 and /BL2 but stored data is not output (hereinafter called “pseudo-read state”). Therefore, the potential of the cell node at which a Low level is stored rises, and thus leading to the occurrence of the stored data corruption.
Further, Japanese Unexamined Patent Application Publication No. 4-205890 discloses a semiconductor storage device in which the driving capability of word line drivers during writing operation is reduced and delayed by a read/write signal (R/W signal) in order to eliminate the necessity of the write recovery time (address delay) that would be otherwise necessary when the semiconductor storage device changes from the write mode to the read mode.